The present invention relates to a semiconductor memory device such as a DRAM and a method of testing the same, and relates, more particularly, to a semiconductor memory device incorporating a circuit for testing a presence or absence of a leakage of charges held in memory cells and a method of testing the same.
There have been carried out various types of tests to semiconductor memory devices including DRAM's or others in order to detect defective products prior to their shipments. These tests are called a die sorting test or the like, which generally include a contact checking, a current value checking of a stand-by current, an operation current, etc., a testing of a DC system including an internal voltage monitor, etc., a function testing for screening defective bits in a memory cell array by variously changing an applied voltage, timing of a voltage application and a writing pattern to the cell array, etc.
This function test includes a leakage test (hereinafter to be referred to as "Cell transfer-gate leak acceleration test") for checking a presence or absence of a leakage of charges held in memory cells. According to this "Cell transfer-gate leak acceleration test", a stress is applied to between a capacitor and a bit line of memory cells thereby to test a presence or absence of a leakage of charges via select transistors of cells. Along with the progress of low voltage, a threshold voltage VTH of a select transistor of each of cells also becomes low. This results in an increase in sub-threshold current. Therefore, it is considered there will be an increasing need of a test for checking a leakage of charges via transistors of cells.
A method of the conventional "Cell transfer-gate leak acceleration test" will be explained below with reference to FIG. 8.
FIG. 8 shows a normal DRAM memory array and its peripheral circuits. Each column has a pair of bit lines BL and /BL, and a memory cell connected to the bit line /BL side and a memory cell connected to the bit line /BL side are connected to different word lines WL. This cell arrangement has been used conventionally for the purpose of increasing the density of high integration and has also been well known.
For carrying out the "Cell transfer-gate leak acceleration test" to the cell array of FIG. 8, at first, data "1" is written into all memory cells M11 to M49, and then any one optional word line connected to the memory cell of the bit line BL side, for example WL1, is started, and data is read out from the memory cells (reference cells in the drawing) M15, M25, M35 and M45 connected to the word line WL1 onto corresponding bit lines BL1, BL2, BL3 and BL4. Thus, the voltage of each of the bit lines BL1, BL2, BL3 and BL4 becomes higher than a pre-charge voltage (VCC/2) and also becomes higher than each voltage of bit lines /BL1, /BL2, /BL3 and /BL4 that hold the pre-charge voltage. This voltage difference is sensed and amplified by a corresponding sense amplifier (S/A), and the voltages of the bit lines BL1, BL2, BL3 and BL4 are set to VCC and the voltages of the bit lines /BL1, /BL2, /BL3 and /BL4 are set to 0 V. With this arrangement, the voltage VCC is applied to between the drain and the source of the select transistor of each memory cell connected to the bit lines /BL1, /BL2, /BL3 and /BL4 side. Thus, a stress is applied to between the source and the drain of the select transistor of each of the memory cells.
In actual practice, this reading operation is executed repeatedly at a predetermined time interval. More specifically, a RAS Only Refresh cycle for selecting the same word line WL1 is executed repeatedly by 2,560 times in a RAS cycle time (tRC=200 .mu.s), for example. As a result, the word line WL1 is selected during a period of 512 ms (=2,560.times.200 .mu.s), and the stress is kept being applied to each memory cell connected to the bit lines /BL1, /BL2, /BL3 and /BL4 side during this period.
FIG. 9 is a cross-sectional structure of a memory cell for explaining a state that a stress is applied to a memory cell. A reference is made to a memory cell M16 structured by a select transistor Q16 and a trench capacitor C16. The source of the select transistor Q16 is connected to the bit line /BL1 that is set to 0 V, and the drain is connected to the trench capacitor C16 held at VCC by the writing of the data "1". Accordingly, the voltage VCC is applied to between the drain and the source of the select transistor Q16 during a 512 ms period. If there is a defect that the sub-threshold current of the transistor Q16 is large, a charge leaks out from the trench capacitor C16.
After the 2,560 times of RAS Only Refresh cycle for selecting the word line WL1 have been completed, a RAS Only Refresh for starting an optional one word line connected to the memory cell of the bit line /BL side, for example, WL2, is executed repeatedly by 2,560 times at a time interval of RAS cycle time (tRC=200 .mu.s). In this RAS Only Refresh cycle, data is read out from the memory cells (reference cells in the drawing) M16, M26, M36 and M46 connected to the word line WL2 onto corresponding bit lines /BL1, /BL2, /BL3 and /BL4 as shown in FIG. 10. Thus, the voltage of each of the bit lines /BL1, /BL2, /BL3 and /BL4 becomes higher than a pre-charge voltage (VCC/2) and also becomes higher than the voltage of each of the bit lines BL1, BL2, BL3 and BL4 that hold the pre-charge voltage. This voltage difference is sensed and amplified by a corresponding sense amplifier (S/A), and the voltages of the bit lines /BL1, /BL2, /BL3 and /BL4 are set to VCC and the voltages of the bit lines BL1, BL2, BL3 and BL4 are set to 0 V. With this arrangement, the voltage VCC is applied to between the drain and the source of the select transistor of each memory cell connected to the bit lines BL1, BL2, BL3 and BL4 side. Thus, a stress is applied to the memory cells.
Last, a data reading operation is carried out for checking a presence or absence of a leakage. In other words, data of all the memory cells are read out by the normal data reading operation, and it is checked whether the value of data read out from each memory cell coincides with an expected value "1" or not. There is no leakage of charge in the memory cell if the value of the read-out data coincides with the expected value "1", and there is a leakage of charge in the memory cell if the value of the read-out data coincides with "0".
However, since this conventional "Cell transfer-gate leak acceleration test" employs a system of controlling a bit line voltage by latching the data read out from the memory cell that becomes a reference cell by the sense amplifier S/A, it is not possible to apply a desired voltage to between the capacitor and the bit line of the cell if the bit line voltage has a value opposite to an expected value because of a poor fixing of the memory cell itself (for example, a defect that the data "0" is held in the memory cell, and the data "1" cannot be written into the memory cell) or due to a line failure that a selected word line itself is not started. Therefore, there arises such an inconvenience that it is not possible to detect accurately a presence or absence of a leakage failure.
Further, when, after a fuse blow, the "Cell transfer-gate leak acceleration test" is applied to a DRAM in which a main array block and a spare word line block are mutually independent and sense amplifiers are provided separately and only one of the blocks is operated in the normal operation, there is the following problem.
There may be a case where one of the two word lines selected by the "Cell transfer-gate leak acceleration test" as described above has been replaced by the spare word line due to the fuse blow. In this case, if the main array block and the spare array block are mutually independent and the sense amplifiers are provided separately, there is no change in the voltage of the bit line within the main array even if the RAS Only Refresh cycle is executed by starting the spare word line. Accordingly, even if the cells within the spare block can be tested, a stress cannot be applied to the cells within the main array. As a result, an accurate leakage test cannot be carried out.